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tm
TE CH
T15M1024A
SRAM
FEATURES
* Low-power consumption - Active: 42mA at 45ns - Stand-by: (CMOS input/output) 0 ~ +70 C = 15uA -40 ~ +85 C = 20uA * 45/55/70/100 ns access time * Equal access and cycle time * Single +5V (10%) Power Supply * TTL compatible , Tri-state output * Common I/O capability * Automatic power-down when deselected * Available in 32-pin SOP ,TSOP-I(8x20mm), TSOP-I(8x13.4mm) and DIP (600 mil) package.
128K X 8 LOW POWER CMOS STATIC RAM
GENERAL DESCRIPTION
The T15M1024A is a very Low Power CMOS Static RAM organized as 131,072 words by 8 bits. That operates on a wide voltage range from +5V (10%) power supply, Fabricated using high performance CMOS technology, Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Data retention is guaranteed at a power supply voltage as low as 1.5V.
BLOCK DIAGRAM
PART NUMBER EXAMPLES
PART NO.
T15M1024A-55D T15M1024A-70H T15M1024A-100P T15M1024A-100N T15M1024A-55DI T15M1024A-70HI T15M1024A-100PI T15M1024A-100NI
PACKAGE CODE
D=SOP H=TSOP-I(8x20) P=TSOP-I(8x13.4) N=DIP (600 mil) D=SOP H=TSOP-I(8x20) P=TSOP-I(8x13.4) N=DIP (600 mil)
Operating Temperature
0 ~ +70 C
Vcc Vss A0 . . . A16 WE OE CE1 CE2
DECODER
CORE ARRAY
-40 ~ +85 C
CONTROL CIRCUIT
DATA I/O
I/O1 .. I/O8
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P. 1
Publication Date: OCT. 2004 Revision:C
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NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
TE CH
T15M1024A
PIN CONFIGURATIONS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4
DIP & SOP
A11 A9 A8 A13 WE CE2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP-I (8x20mm) & (8x13.4mm)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS A0 ~ A16 Address inputs I/O1~I/O8 Data inputs/outputs
CE1 ,CE2 Chip enable WE
SYMBOL DESCRIPTIONS
OE
Output enable input Power supply Ground No connection
VDD VSS NC
Write enable input
TM Technology Inc. reserves the right to change products or specifications without notice.
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Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on Any Pin Relative to Gnd Power Dissipation Storage Temperature Temperature Under Bias SYM VR PD TSTG IBIAS MIN. -0.5 -55 0/-40 MAX. +7 V 0.7 +150 +70/+85 UNIT V W C C
*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
CE2 WE OE CE 1 H X X X X L X X L H H L L H H H L H L X *Note: X = Don't Care, L = Low, H = High DATA High-Z High-Z Data Out High-Z Data In MODE
Standby Standby
Active, Read Active, Output Disable Acitve, Write
TM Technology Inc. reserves the right to change products or specifications without notice.
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Publication Date: OCT. 2004 Revision:C
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T15M1024A
OPERATING CHARACTERISTICS
(Vcc = +5V / 10%, Gnd = 0V, Ta = 0 ~ +70 C / -40C ~ 85C)
PARAMETER Input Leakage Current Output Leakage Current SYM. ILI TEST CONDITIONS Vcc = Max, VIN = Gnd to Vcc
CE1 = VIH or CE2= VIL
-45
-55
-70
-100
UNIT
Min Max Min Max Min Max Min Max
-
1
-
1
-
1
-
1
uA
ILO
or OE = VIH or WE = VIL VOUT= Gnd to Vcc
CE1 = VIL,CE2= VIH,
-
1
-
1
-
1
-
1
uA
Operating Power Supply Current
ICC
WE =VIH, OE = VIH , VIN = VIH or VIL, IOUT=0mA
-
2
-
2
-
2
-
2
mA
ICC1 Average Operating Current ICC2
Cycle time=1us, 100% duty, IOUT=0mA, CE1 0.2V, CE2 VCC-0.2V, VIN 0.2V Cycle time=min, 100% duty, IOUT=0mA, CE1 = VIL,CE2= VIH , VIN = VIH or VIL
CE1 =VIH CE2= VIL CE1 Vcc-0.2V,
0 to 70C -40 to 85C
-
3
-
3
-
3
-
3
mA
-
42
-
40
-
35
-
25
mA
Standby Power Supply Current (TTL Level)
I SB
-
0.5
-
0.5
-
0.5
-
0.5
mA
Standby Power Supply Current (CMOS Level)
I SB1
CE2 VCC-0.2V or CE2 0.2V VIN 0.2V or VIN Vcc-0.2V
-
15
-
15
-
15
-
15
uA
-
20
-
20
-
20
-
20
uA V V
Output Low Voltage VOL Output High Voltage VOH
I OL = 2.1mA I OH = -1.0 mA
- 0.4 2.4 -
- 0.4 2.4 -
- 0.4 2.4 -
- 0.4 2.4 -
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 4
Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
RECOMMENDED OPERATING CONDITIONS (Ta = 0 ~ +70 C /-40C to 85C**)
PARAMETER Supply Voltage Input Voltage SYM Vcc Gnd MIN 4.5 0.0 2.2 -0.3 MAX 5.5 0.0 Vcc+0.3 0.6 UNIT V V V V
VIH VIL
CAPACITANCE
(f = 1 MHz, Ta = 25C,)
PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VIN =VOUT = 0V MAX. 6 8 UNIT pF pF
C IN C I/O
Note: This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0.6V to 2.2V 5.0 ns 1.5V C L =30pF+1TTL Load(45ns/55ns/70ns) C L =100pF+1TTL Load(Load for 100ns)
AC TEST LOADS AND WAVEFORM
TTL DQ RL 50 ohm CL* Z0 = 50 ohm Vt =1.5V CL 30 pF
Fig.A * Including Scope and Jig Capacitance
Fig.B Output Load Equivalent
TM Technology Inc. reserves the right to change products or specifications without notice.
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Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
AC CHARACTERISTICS
(Vcc = +5V / 10%, Gnd = 0V, Ta = 0 ~ +70 C /-40C to 85C)
(1) READ CYCLE
PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z SYM. tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ 45 10 7 5 -45
Min Max
-55
Min Max
-70
Min Max
-100
Min Max
UNIT ns ns ns ns ns ns ns ns ns
45 45 22 15 15
55 10 10 5 -
55 55 25 20 20
70 10 10 5 -
70 70 35 25 25
100 10 10 5 -
100 100 50 30 30
(2)WRITE CYCLE
PARAMETER Write Cycle Time Chip Enable to Write End Address Valid to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End SYM. tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW 45 40 40 0 35 0 20 0 5 -45
Min Max
-55
Min Max
-70
Min Max
-100
Min Max
UNIT ns ns ns ns ns ns ns ns ns ns
15 -
55 50 50 0 45 0 25 0 5
20 -
70 60 60 0 50 0 30 0 5
25 -
100 80 80 0 70 0 40 0 5
30 -
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 6
Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
TIMING WAVEFORMS READ CYCLE 1
(Address Controlled)
tRC
Address
t AA tOH
DOUT
Previous Data Valid
Data Valid
READ CYCLE 2
(Chip Enable Controlled)
CE1
CE2
t ACE tOLZ tOHZ
D
OUT
DON'T CARE UNDEFINED
Notes (READ CYCLE) : 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device and from device to device interconnection. 5. Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE1 =VIL .
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 7
Publication Date: OCT. 2004 Revision:C
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Add ress CE1
TE CH
( WE Controlled)
tWC
T15M1024A
WRITE CYCLE 1
tAW tCW
tWR
CE2
tA S tWP
WE
tWHZ tOW
DOUT
H ig h-Z
tDW tDH
DIN
H ig h -Z
WRITE CYCLE 2
( CE Controlled)
tWC
Add ress
tAW tCW tWR
CE1
t AS
CE2
tWP
WE
DOUT
H ig h -Z
tDW tDH
D IN
H ig h -Z
H ig h -Z
D O N 'T C AR E U N D E F IN E D
NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low CE1 , a high CE2 and a low WE . A write begins at the lateat transition among CE1 goes low, CE2 going high and WE going low. A write end at the earliest transition among CE1 going high, CE2 going low and WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE1 going low or CE2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. TM Technology Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
DATA RETENTION CHARACTERISTICS
PARAMETER VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time SYM. VDR ICCDR tCDR tR TEST CONDITION CE1 VDD -0.2V CE2 0.2V VIN Vcc -0.2V or VIN 0.2V MIN. 1.5 0 tRC MAX. 5* UNIT V uA ns ns
* 0 ~ +70 C / -40 ~ +85 C,VCC=3V
DATA RETENTION WAVEFORM
(Ta = 0 ~ +70 C /-40C to 85C)
Data Retention M ode
V CC
V cc_typ
t
V D R > 1.5V
t
Vcc_TYP R
CD R
CE1
CE1>VCC-0.2V
V IH V IH
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 9
Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
PACKAGE DIMENSIONS 32-LEAD SOP
e1 17
E HE
Detail F 1 D A2 S y Seating Plane Dimension in inches min. typ. max 0.118 0.004 0.101 0.106 0.111 0.014 0.016 0.020 0.006 0.008 0.012 0.805 0.817 0.440 0.445 0.450 0.044 0.050 0.056 0.546 0.556 0.556 0.023 0.031 0.039 0.047 0.055 0.063 0.036 0.004 0 10 Dimension in mm min. typ. max. 3.00 0.10 2.57 2.69 2.82 0.36 0.41 0.51 0.15 0.20 0.31 20.45 20.75 11.18 11.30 11.43 1.12 1.27 1.42 13.87 14.12 14.38 0.58 0.79 0.99 1.19 1.40 1.60 0.91 0.10 0 10 e A1 See Detail F A LE b 16 L e1 C
Symbol A A1 A2 b C D E e HE L LE S y
Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 10
Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
PACKAGE DIMENSIONS 32-LEAD TSOP (8x20mm)
SYMBOL
A A1 A2 b C D Db E L L1
DIMENSIONS IN INCHES MIN -0.002 0.035 0.007 0.004 NOM 0.040 0.008 0.006 0.787 TYP 0.724 TYP 0.315 TYP 0.024 0.032 TYP 0~12 MAX 0.047 0.006 0.041 0.011 0.008
DIMENSIONS IN MM MIN 0.05 0.90 0.17 0.10 NOM 1.00 0.20 0.15 20.00 TYP 18.40 TYP 8.00 TYP 0.610 0.813 TYP 0~12 MAX 1.20 0.15 1.05 0.27 0.21
0.020
0.028
0.598
0.622
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 11
Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm)
SYMBOL A A1 A2 b C D E HD e L L1 y
Dimension in inches 0.044(MAX) 0.0040.002 0.041(MAX) 0.0080.004 0.0060.001 0.4650.008 0.3150.004 0.5280.008 0.020(TYP.) 0.0200.004 0.0310.008 0.002(MAX) 0 ~ 5
Dimension in mm 1.10(MAX) 0.050.05 1.02(MAX) 0.200.10 0.150.02 11.80.2 8.00.1 13.40.2 0.5(TYP.) 0.50.1 0.80.2 0.05(MAX) 0 ~ 5
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 12
Publication Date: OCT. 2004 Revision:C
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TE CH
T15M1024A
PACKAGE DIMENSIONS 32-LEAD DIP (600mil)
C E 3.60 A1 A2 Publication Date: OCT. 2004 Revision:C
c
32
17
1
16
D
L
A
SEATING PLANE
e
b1
b
Symbol
A A1 A2 b b1 C D E e e1 L
Dimension in inches Min Nom Max 0.200 0.015 0.142 0.150 0.158 0.014 0.018 0.022 0.056 0.060 0.064 0.008 0.010 0.014 1.642 1.650 1.658 0.527 0.535 0.543 0.100 0.118 0.600 0.130 -
Dimension in mm Min Nom Max 5.08 0.38 3.61 3.81 4.01 0.36 0.46 0.56 1.42 1.52 1.62 0.20 0.25 0.35 41.71 41.91 42.11 13.40 13.60 13.80 2.54 15.24 3.30
0.142 3.00 0 ~ 15
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 13
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